circuit transfer :
  module transfer :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, cardio : { flip card_group_data : UInt<2>, flip card_group_cmd : UInt<1>, group_card_state : UInt<1>, group_card_result : UInt<8>}, flip emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[transfer.scala 31:19]
    reg io_emitterio_fpga_cim_data_r : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_emitterio_fpga_cim_data_r <= io.cardio.card_group_data @[Reg.scala 29:22]
    io.emitterio.fpga_cim_data <= io_emitterio_fpga_cim_data_r @[transfer.scala 33:32]
    reg io_emitterio_fpga_cim_cmd_r : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_emitterio_fpga_cim_cmd_r <= io.cardio.card_group_cmd @[Reg.scala 29:22]
    io.emitterio.fpga_cim_cmd <= io_emitterio_fpga_cim_cmd_r @[transfer.scala 34:32]
    reg io_cardio_group_card_result_r : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_cardio_group_card_result_r <= io.emitterio.cim_fpga_result @[Reg.scala 29:22]
    io.cardio.group_card_result <= io_cardio_group_card_result_r @[transfer.scala 35:34]
    reg io_cardio_group_card_state_r : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_cardio_group_card_state_r <= io.emitterio.cim_fpga_state @[Reg.scala 29:22]
    io.cardio.group_card_state <= io_cardio_group_card_state_r @[transfer.scala 36:34]

